1. Field of the Invention
This invention relates to a memory circuit having an error correcting function, and more particularly, to a memory circuit which is tough to a multi-bit error in which a plurality of bit errors generates locally.
2. Description of the Prior Art
FIG. 7 is a circuit configuration for illustrating a conventional memory circuit having an error correcting function (hereinafter, simply called memory circuit). In FIG. 7, a reference numeral 11 represents a memory cell array. A reference numeral 12 represents a memory cell. A reference numeral 13 represents a sense amplifier circuit. A reference numeral 14 represents an ECC (Error Check and Correction) circuit. In such a memory circuit, parity bits of n bits are added to data of m bits, where n represents a positive integer which is not less than one, and m represents a positive integer which is not less than two. When an error occurs in at least one bit on carrying out a read/write operation for the memory cell array 11, the ECC circuit 14 carries out a correction of the error bit.
Next, the description will be given of an operation of the memory circuit illustrated in FIG. 7.
In the example being illustrated, the memory circuit illustrated in FIG. 7 has m=4 and n=3. BCH codes are used as error correcting codes. The parity bits of three bits are added to the data of four bits. The read/write operation is carried out for the memory cell array 11 in unit of the data of seven bits in sum. When a specific one of word lines is selected as a selected word line and the read/write operation is carried out for the memory cell array 11, the data of 7 bits are read from and written to seven memory cells 12 which are adjacent to one another. In FIG. 7, the adjacent seven memory cells will be collectively called a memory block.
On a read operation, the data of 7 bits are read out of each of a plurality of memory blocks which correspond to the selected word line. The data of 7 bits are supplied to the ECC circuits 14 through the sense amplifier circuits 13, respectively. In other words, the data of 7 bits are supplied to each of the ECC circuits 14. When an error bit or error bits exist in the data of 7 bits, each of the ECC circuits 14 corrects the data in accordance with the parity bits to output the data of 4 bits as read data.
On the other hand, writing data of 4 bits are supplied to each of the ECC circuits 14 on a write operation. Each of the ECC circuits 14 adds the parity bits of three bits to the writing data to output writing data of 7 bits. Through the sense amplifier circuits 13, the writing data of 7 bits are written to the memory blocks which correspond to the selected word line, respectively.
FIG. 8 shows a view for illustrating a memory block of an SRAM. The memory block has seven memory cells 12a to 12g. The memory cells 12a to 12g are connected to the sense amplifiers 13a to 13g through bit lines, respectively. Through the sense amplifiers 13a to 13d, datum bits are read from and written to the memory cells 12a to 12d, respectively. Furthermore, parity bits are read from and written to the memory cells 12e to 12g, respectively, through the sense amplifiers 13e to 13g. 
The description will be given of a read/write operation for the SRAM illustrated in FIG. 8. At first, the data of 7 bits are read out of the SRAM. At that time, the data of 7 bits are supplied to the ECC circuits, respectively, in order to carry out the error check and correction, as described above. When the data of 7 bits have error bits whose number is not less than two, errors may be included in the corrected datum bits and the corrected parity bits. Under the circumstances, each of the ECC circuits outputs 2 bits error detection flag. Responsive to the 2 bits error detection flag, the SRAM is reset.
On the other hand, each of the ECC circuits does not output the 2 bits error detection flag when 1 bit error occurs. Each of the ECC circuits corrects the datum bits or the parity bits to produce corrected datum bits or corrected parity bits. Thereafter, that processing continues with using the corrected datum bits. The corrected datum bits and the corrected parity bits (corrected data of 7 bits) are written in the SRAM. Furthermore, the data of 7 bits are again read out of the SRAM to be processed in a similar manner described above, when it is necessary to read the data out of the SRAM.
FIG. 9 shows a view for illustrating a memory block of a DRAM. The memory block has seven memory cells 121 to 127. The memory cells 121 to 127 are connected to the sense amplifiers 131 to 137 through bit lines, respectively. Through the sense amplifiers 131 to 134, datum bits are read from and written to the memory cells 121 to 124, respectively. Furthermore, parity bits are read from and written to the memory cells 125 to 127, respectively, through the sense amplifiers 135 to 137.
In the DRAM illustrated in FIG. 9, the error check and correction is carried out in a manner similar to the SRAM illustrated in FIG. 8.
By the way, the above-mentioned data error (bit error) may locally occur. Such a data error may be called a soft error. More particularly, a pair of electron and hole generates when alpha ray or neutron ray is plunged into the semiconductor substrate. The alpha ray may be released from a semiconductor material of the semiconductor substrate. The neutron ray occurs in nature. When the electron is absorbed into a latch node of the memory cell, the datum is destroyed in the memory cell so that the soft error occurs. In the other words, the soft error is an error in which the data are locally destroyed in only parts into which the alpha ray or the neutron ray is plunged. On the basis of the cause of error, the soft error will be called an alpha ray soft error or a neutron ray soft error.
A plurality of soft errors may occur locally and simultaneously by one plunge of the alpha ray or the neutron ray. The above-mentioned errors will be called a multi-bit soft error.
Recently, the amount of the accumulated charge becomes low in a memory node of the memory cell in the SRAM, as a semiconductor integrated circuit becomes fine. For example, the amount of the accumulated charge is reduced to a level of 5f-coulombs in 0.18 μm-generation. In as much as electrons, which are generated in the semiconductor substrate by each particle of the alpha ray and the neutron ray, have charges of 20 f-coulombs to 200 f-coulombs, there is a growing possibility that errors simultaneously occur in adjacent memory cells by the plunge of one particle.
Inasmuch as the data of (m+n) bits are read out of the memory cells of (m+n) that are adjacent to one another, in the conventional memory circuit, there is a drawback in which makes it impossible to correct the errors when the multi-bit soft error occurs in which a plurality of bit errors generates locally and simultaneously, as described above. In other words, there is a drawback in which makes it impossible to correct the errors when bit errors having a bit number greater than a correctable one occur simultaneously due to the multi-bit soft error.
For example, there is a drawback in which it is impossible to correct the errors when the errors simultaneously occur in two bits due to the multi-bit soft error in the adjacent data of 7 bits as described above.